As microprocessor systems increase in size and speed, there is need for larger and faster memory arrays. These high-speed memory arrays may contain a large number of memory cells. However, as the number of memory elements increases, the time needed to read and/or write to the individual memory cells may also increase. This may be due to the fact that as the number of memory elements increases in an individual array, the length of the wordline between the supply voltage and the individual memory cells may also increase. The increased length of the wordline may directly relate to an increase in the resistance of the wordline. Therefore, as the size of the memory array increases so may the required voltage needed to read the individual memory cells. Additionally, in large memory arrays, the capacitance of the wordline may require an increase in the time required charge to the desired level in order to access a given memory cell. The increase in the time required to charge the wordline may lead to a large cycle time, which may directly limit the access time for the memory. Additionally, the increase in the time required to charge the capacitance may also limit the length of the wordline. As the length of the wordline increases so does the resistance value of the wordline wire. Therefore, the time required to charge the capacitance may be limited by the large RC value associated with a longer wire.
For example, FIG. 1A shows a representative prior art arrangement whereby wordline 100 having wordline capacitance Cwl is coupled to high voltage charge pump 102 by way of switch circuit 104. As shown in FIG. 1B, at time t1, charge pump 102 goes into regulation providing pump current Ipump at charge pump output node 106. In order for wordline voltage Vwl to recover to Vreg, switch circuit 104 connects wordline 100 to charge pump output node 106 at time t2 (causing the momentary decrease in Vreg due to charge sharing). At time t3, wordline voltage Vwl reaches target wordline voltage Vreg. In this arrangement, the wordline recovery time (Δt=t3−t2) is determined as Eq(1):Δt=(Cwl×Vreg)/Ipump  Eq(1)
There have been many attempts at improving the wordline recovery time Δt. One such attempt relies upon using what is referred to as stacked memory cell in which a large single array is broken into a number of smaller arrays thereby reducing the resistive/capacitive loading (i.e., RC time constant) of the array as a whole. However, this approach requires a substantial increase in the amount of silicon used since the amount of silicon required increases proportionally with the number of memory arrays included in the stacked architecture as does manufacturing costs. Other attempts to reduce wordline time recovery rely upon simply increasing charge pump current Ipump. Unfortunately, in order to increase the capacity of high voltage charge pump 102, not only does the size of high voltage charge pump 102 increase but charge pump 102 operates at a higher output voltage Vref and is therefore operating less efficiently. Each of these factors contribute in their own way to an overall increase in power consumption of the memory device as well as the amount of silicon required for fabrication of the larger capacity charge pumps.
Therefore, what is required is a system for reducing wordline recovery time.